Journal Papers
[J4] Upper and Lower Bounds on the Computational Complexity of Polar Encoding and Decoding
C. G. Blake and F. R. Kschischang,
IEEE Trans. Info. Theory,
vol. 65, pp. 5656–5673, Sep. 2019. doi:
10.1109/TIT.2019.2917683
[J10] Energy, Latency, and Reliability Tradeoffs in Coding Circuits
C. G. Blake and F. R. Kschischang,
IEEE Trans. Info. Theory,
vol. 65, pp. 935–946, Feb. 2019. doi:
10.1109/TIT.2018.2865701
[J12] Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations
F. Leduc-Primeau, F. R. Kschischang, and W. J. Gross,
IEEE Trans. Commun.,
vol. 66, pp. 932–946, Mar. 2018. doi:
10.1109/TCOMM.2017.2778247
[J16] On the VLSI Energy Complexity of LDPC Decoder Circuits
C. G. Blake and F. R. Kschischang,
IEEE Trans. Info. Theory,
vol. 63, pp. 2781–2795, May 2017. doi:
10.1109/TIT.2017.2673805
[J26] Energy Consumption of VLSI Decoders
C. G. Blake and F. R. Kschischang,
IEEE Trans. Info. Theory,
vol. 61, pp. 3185–3198, Jun. 2015. doi:
10.1109/TIT.2015.2421520
[J54] Power Reduction Techniques for LDPC Decoders
A. Darabiha, A. C. Carusone, and F. R. Kschischang,
IEEE J. Solid State Circuits,
vol. 43, pp. 1835–1845, Aug. 2008. doi:
10.1109/JSSC.2008.925402
[J56] Block-Interlaced LDPC Decoders with Reduced Interconnect Complexity
A. Darabiha, A. C. Carusone, and F. R. Kschischang,
IEEE Trans. Circuits and Sys. II,
vol. 55, pp. 74–78, Jan. 2008. doi:
10.1109/TCSII.2007.905328
[J59] Architecture and Implementation of an Interpolation Processor for Soft-decision Reed-Solomon Decoding
W. J. Gross, F. R. Kschischang, and P. G. Gulak,
IEEE Trans. VLSI Sys.,
vol. 15, pp. 309–318, Mar. 2007. doi:
10.1109/TVLSI.2007.893609
[J64] Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes
W. J. Gross, F. R. Kschischang, and P. G. Gulak,
IEEE Trans. Commun.,
vol. 54, pp. 1224–1234, Jul. 2006. doi:
10.1109/TCOMM.2006.877972
[J74] Towards a VLSI Architecture for Interpolation-based Soft-Decision Reed-Solomon Decoders
Conference Papers
[C9] Energy Complexity of Polar Codes
C. G. Blake and F. R. Kschischang, in
Proc. IEEE Int. Symp. on Info. Theory,
Barcelona, Spain, Jul. 10, 2016–Jul. 15, 2016, pp. 810–814. doi:
10.1109/ISIT.2016.7541411
[C13] Scaling Rules for the Energy of Decoder Circuits
C. G. Blake and F. R. Kschischang, in
Proc. IEEE Int. Symp. on Info. Theory,
Hong Kong, Jun. 14, 2015–Jun. 19, 2015, pp. 1437–1441, selected for semi-plenary presentation. doi:
10.1109/ISIT.2015.7282693
[C16] Energy Optimization of LDPC Decoder Circuits with Timing Violations
F. Leduc-Primeau, F. R. Kschischang, and W. J. Gross, in
Proc. IEEE Int. Conf. Commun.,
London, UK, Jun. 8–12, 2015, pp. 412–417. doi:
10.1109/ICC.2015.7248356
[C25] Energy of Decoding Algorithms
C. Blake and F. R. Kschischang, in
Proc. 13th Canadian Workshop on Information Theory,
Toronto, ON, Jun. 18, 2013–Jun. 21, 2013, pp. 1–5. doi:
10.1109/CWIT.2013.6621582
[C53] A 3.3-Gbps Bit-Serial Block-interlaced Min-Sum LDPC Decoder in 0.13 µm CMOS
A. Darabiha, A. Chan Carusone, and F. R. Kschischang, in
Proc. IEEE Conf. Custom Integ. Circ,
San Jose, CA, Sep. 2007, pp. 459–462. doi:
10.1109/CICC.2007.4405773
[C62] A Bit-Serial Approximate Min-Sum LDPC Decoder and FPGA Implementation
A. Darabiha, A. Chan Carusone, and F. R. Kschischang, in
Proc. 2006 IEEE Int. Symp. Circuits and Syst.,
Kos, Greece, May 2006. doi:
10.1109/ISCAS.2006.1692544
[C71] Multi-Gbit/sec Low-Density Parity-Check Decoders with Reduced Interconnect Complexity
A. Darabiha, A. Chan Carusone, and F. R. Kschischang, in
IEEE Int. Symp. Circuits and Systems,
Kobe, Japan, May 2005, pp. 5194–5197. doi:
10.1109/ISCAS.2005.1465805
[C82] An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
W. J. Gross, F. R. Kschischang, and P. G. Gulak, in
Proc. 12th Annual IEEE Symp. on Field-Programmable Custom Computing Machines,
Napa, CA, Apr. 2004, pp. 310–311. doi:
10.1109/FCCM.2004.16
[C94] A VLSI Architecture for Interpolation in Soft-Decision List Decoding of Reed-Solomon Codes
W. J. Gross, F. R. Kschischang, R. Koetter, and P. G. Gulak, in
Proc. 2002 IEEE Workshop on Signal Processing Systems,
San Diego, CA, Oct. 2002. doi:
10.1109/SIPS.2002.1049682
Updated: Mon Jan 20 17:04:01 EST 2020